1. Field of the Invention
This invention relates to integrated circuit (IC) fabrication technology, and more particularly, to a method of forming a self-aligned silicide (also called salicide) structure in IC fabrication.
2. Description of the Related Art
As IC fabrication technologies advance to the submicron level of integration, the semiconductor components in the ICs are now fabricated having very small line widths, contact surfaces, and junction depths. When a polysilicon-based structure is downsized, it will undesirably result in an increase in resistance since the resistance is proportional to the cross sectional area. As a consequence, all the RC delay circuits in the IC device are increased in time constant, thus undesirably providing an increased RC delay.
One solution to the foregoing problem is to use the so-called salicide (acronym for self-aligned silicide) technology to form a salicide structure over the polysilicon-based structure, which can help increase the conductivity. The salicide structure can be self-aligned to the predefined locations and dimensions without the use of photolithography. Conventionally, titanium silicide (TiSi.sub.x) is the semiconductor material most widely utilized to form a salicide structure.
FIGS. 1A-1D are schematic diagrams used to depict the steps involved in a conventional method for forming a salicide structure in an IC device
Referring first to FIG. 1A, in the first step, a semiconductor substrate 100 is prepared. This substrate 100 is then formed with a plurality of isolation structures 102 at predefined locations. Next, a MOS structure is formed within the area defined by the isolation structures 102 over the substrate 100, which includes a gate oxide layer 104, a polysilicon-based gate structure 106, a pair of source/drain regions 110, and a sidewall-spacer structure 108.
Referring next to FIG. 1B, in the subsequent step, a sputtering process is performed to form a metallization layer 112 over the entire top surface of the wafer, covering all the exposed surfaces of the source/drain regions 110 and the polysilicon-based gate structure 106. This metallization layer 112 can be formed, for example, from tungsten.
Referring further to FIG. 1C, in the subsequent step, an RTP (Rapid Thermal Process) is performed on the wafer to cause the metal atoms in the metallization layer 112 to react with the silicon atoms in the source/drain regions 110 and the polysilicon-based gate structure 106. As a result of this process, silicide layers 114 are formed at the contact surface between the metallization layer 112 and the source/drain regions 110 as well as at the contact surface between the metallization layer 112 and the polysilicon-based gate structure 106.
Referring next to FIG. 1D, in the subsequent step, a wet-etching process is performed to remove all the unreacted part of the metallization layer 112 (FIG. 1C) until the silicide layers 114 are exposed. Since these silicide layers 114 can be aligned to the intended locations without the use of photolithography, they are customarily referred to as a self-aligned silicide structure, or a salicide structure.
As the fabrication advances to the submicron level of integration, however, the polysilicon-based gate structure 106 is reduced to a very small size. This results in an increased stress and a reduced nucleation site for the salicide structure 114 formed over the polysilicon-based gate structure 106. This, in turn, undesirably causes a change in the content of the silicon atoms in the silicide; i.e., the value of x in TiSi.sub.x is changed, resulting in an undesired increase to the sheet resistance of the salicide structure. As a consequence, the performance of the overall IC device is degraded.